FCCM 2025 Accepted Paper List
| Paper ID | Format | Title | Authors |
|---|---|---|---|
| 6 | Short | LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation | Zixi Zhang (University of Cambridge), Balint Szekely (Imperial College London), Pedro Gimenes (Imperial College London), Greg Chadwick (lowRISC), Hugo McNally (lowRISC), Jianyi Cheng (University of Edinburgh), Robert Mullins (University of Cambridge), Yiren Zhao (Imperial College London) |
| 16 | Long | Moyogi: A Memory-centric Accelerator for Low-Latency Random Forest Inference on Embedded Devices | Alessandro Verosimile (Politecnico di Milano), Francesco Peverelli (Politecnico di Milano), Marco D. Santambrogio (Politecnico di Milano) |
| 49 | Long | FPGA-based Approximate Multiplier for FP8 | Ruiqi Chen (Vrije Universiteit Brussel), Yangxintong Lyu (Vrije Universiteit Brussel), Han Bao (Vrije Universiteit Brussel), Jiayu Liu (University College London), Yanxiang Zhu (VeriMake Innovation Lab), Shidi Tang (Southeast University), Ming Ling (Southeast University), Bruno da Silva (Vrije Universiteit Brussel) |
| 50 | Long | Banked Memories for Soft SIMT Processors | martin langhammer (Altera, Imperial College London), George A. Constantinides (Imperial College London, UK) |
| 51 | Long | HighWave: Large-scale High-Bandwidth Wave Simulations on FPGAs | Dimitrios Gourounas (The University of Texas at Austin), Austin G. James (The University of Texas at Austin), Bagus Hanindhito (The University of Texas at Austin), Arash Fathi (ExxonMobil), Lizy K. John (The University of Texas at Austin), Andreas Gerstlauer (The University of Texas at Austin) |
| 60 | Long | RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs | Jiho Kim (Georgia Institute of Technology), Cong (Callie) Hao (Georgia Institute of Technology) |
| 74 | Short | HP-FFT: A General High-Performance FFT Generator Using High-Level Synthesis | Chengyue Wang (UCLA), Jiahao Zhang (UCLA), Yingquan Wu (Tenafe, Inc.), Jason Cong (UCLA) |
| 81 | Long | InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs | Zifan He (University of California, Los Angeles), Anderson Truong (University of California, Los Angeles), Yingqi Cao (University of California, San Diego), Jason Cong (University of California, Los Angeles) |
| 82 | Long | Efficiency, Expressivity, and Extensibility in a Close-to-Metal NPU Programming Interface | Erika Hunhoff (University of Colorado, Boulder), Joseph Melber (AMD), Kristof Denolf (AMD), Andra Bisca (AMD), Samuel Bayliss (AMD), Stephen Neuendorffer (AMD), Jeff Fifield (AMD), Jack Lo (AMD), Phil James-Roxby (AMD), Eric Keller (University of Colorado, Boulder), Pranathi Vasireddy (AMD) |
| 84 | Long | IceSpy: Reconfigurable Edge Accelerator for Scalable and Private Structural Health Monitoring | Alexandra Zhang Jiang (University of California, Irvine), Jonathan Ta (University of California, Irvine), Yuqiao Li (University of California, Irvine), Zhou Li (University of California, Irvine), Nalini Venkatasubramanian (University of California, Irvine), Monica D. Kohler (California Institute of Technology), Sang-Woo Jun (University of California Irvine) |
| 99 | Long | HBMex: An Attachment for Nonbursting Accelerators to Enhance HBM Performance | Canberk Sonmez (EPFL), Mohamed Shahawy (EPFL), Paolo Ienne (EPFL) |
| 102 | Long | AutoNTT: Automatic Architecture Design and Exploration for Number Theoretic Transform Acceleration on FPGAs | Dilshan Sampath Kumarathunga Then Kuttiyage (Simon Fraser University), Qilin Hu (Hunan University), Zhenman Fang (Simon Fraser University) |
| 103 | Long | Chronbench: An Incremental HDL Benchmark Suite | Zakary Nafziger (University of British Columbia), Steve Wilton (University of British Columbia) |
| 109 | Long | N-TORC: Native Tensor Optimizer for Real-time Constraints | Suyash Vardhan Singh (University of South Carolina), Iftakhar Ahmad (University of South Carolina), Miaoqing Huang (University of Arkansas), David Andrews (University of Arkansas), Austin Downey (University of South Carolina), Jason D. Bakos (University of South Carolina) |
| 114 | Long | High Throughput Matrix Transposition on HBM-Enabled FPGAs | Yang Yang (University of Southern California), Kyle Tseng (University of Southern California), Viktor Prasanna (University of Southern California), Rajgopal Kannan (DEVCOM Army Research Lab) |
| 121 | Short | FREEDOM: FPGA-based Hardware Redaction Emulator | Benjamin Carrion Schaefer (The University of Texas at Dallas), Chaitali Gajanan Sathe (The University of Texas at Dallas), Yiorgos Makris (The University of Texas at Dallas) |
| 129 | Long | Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox | Shashwat Shrivastava (EPFL), Stefan Nikolić (University of Novi Sad), Sun Tanaka (The University of Tokyo), Chirag Ravishankar (AMD), Dinesh Gaitonde (AMD), Mirjana Stojilovic (EPFL) |
| 141 | Long | Transfer Learning on the Edge for a Wireless Application Using an SoC Platform | Yiyue Jiang (Northeastern University), John Dooley (Maynooth University), Aidan Edward Colgan (Maynooth University), Zhilin Ren (Northeastern University), Jonathan Guimaraes Ribeiro (Maynooth University), Miriam Leeser (Northeastern University) |
| 148 | Long | Efficient and Distributed Computation of Electron Repulsion Integrals on AI Engines | Johannes Menzel (Paderborn University), Christian Plessl (Paderborn University) |
| 158 | Long | An Efficient FPGA-based Hardware Accelerator of Fully Quantized Mamba-2 | Kailing Zhou (Sun Yat-sen University), Han Jiao (Sun Yat-sen University), Wenjin Huang (Sun Yat-sen University), Yihua Huang (Sun Yat-sen University) |
| 173 | Long | NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference | Marta Andronic (Imperial College London, UK), George A. Constantinides (Imperial College London, UK), Marta Andronic (Imperial College London) |
| 233 | Long | ITERA-LLM: Boosting Sub-8-Bit Large Language Model Inference Through Iterative Tensor Decomposition | Yinting Huang (Imperial College London), Keran Zheng (Imperial College London), Zhewen Yu (Imperial College London), Christos-Savvas Bouganis (Imperial College London) |
| 235 | Long | A partitioning-based CAD flow for interposer-based multi-die FPGAs | Mahesh A. Iyer (Altera), Andrew Kahng (University of California San Diego), Jason Luu (Intel), Bodhisatta Pramanik (University of California San Diego), Kristofer Vorwerk (Altera), Grace Zgheib (Altera) |
| 246 | Long | SMART: High-Performance SAR ATR through Model-Architecture Co-Design on FPGA | Sachini Wickramasinghe (University of Southern California), Yi-Chien Lin (University of Southern California), Cauligi Raghavendra (University of Southern California), Viktor Prasanna (University of Southern California) |
| 342 | Short | SoftCUDA: Running CUDA on Softcore GPU | Chihyo Ahn (Georgia Institute of Technology), Ruobing Han (Georgia Institute of Technology), Udit Subramanya (Georgia Institute of Technology), Jisheng Zhao (Georgia Institute of Technology), Blaise Tine (University of California, Los Angeles), Hyesoon Kim (Georgia Tech) |
| 402 | Long | NoH: NoC Compilation in High Level Synthesis | Jake Ke (UCLA), Sihao Liu (UCLA), Licheng Guo (RapidStream Design Automation, Inc.), Zifan He (University of California, Los Angeles), Suhail Basalama (University of California, Los Angeles), Linghao Song (Yale University), Yuze Chi (RapidStream Design Automation, Inc.), Jason Cong (UCLA), Tony Nowatzki (UCLA), Huifeng Ke (University of California, Los Angeles) |